Staff/Principal Engineer – ASIC Digital Design

Design and develop RTL in Central Engineering team for products which includes blocks such as wakeup sequencing, calibration logic, I3C/I2C protocol, interrupt controller, EEPROM, MCU integration etc. Work with Pre/Post-silicon verification teams to test, debug and root-cause RTL simulation/Silicon/FPGA failures. RTL development experience Good knowledge of digital logic design, IP/SoC architecture and microarchitecture Experience Working knowledge of Synthesis, STA, Lint & CDC Experience in high speed FPGA RTL porting, IO mapping, synthesis, timing closure is a plus The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams. PhD, M.S./M.Tech, BS/BE (Electronics) Experience Required: 6+ Years