Senior Silicon Design Engineer (STA)

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THE ROLE: 

We are looking for for a gifted and motivated engineer to join the team in Singapore to support and enable Static Timing Analysis (STA) in our designs.

Static Timing Analysis (STA) compliments the functional simulation and is a method to validate the timing performance of a design. The STA tool breaks down the design into timing paths, calculates the signal propagation delay along each path, then checks for timing violations within and at interfaces of the design. With STA as part of the design flow, both functionality and timing can be signed off with confidence.

The main responsibilities of this role include timing characterization using state-of-the-art EDA tools, to develop and perform quality checks on these models before consumption for timing analysis at higher levels. The macros that require timing characterization will include both traditional mixed signal circuits and complex standard cells. These timing models will enable hierarchical STA runs that significantly boosts timing verification coverage. The engineer will work as part of a team in close cooperation with the design automation team to develop and enhance the characterization and regression platforms. In this highly visible role, the engineer will be working on multi disciplines, with the critical impact on getting functional products to market quickly.
Job Description

KEY RESPONSIBILITIES:

• Responsible for developing timing models (NLDM, CCS and LVF) for advanced technology nodes mixed signal circuits and complex standard cells.
• Responsible for working with various stakeholders (design, layout and STA team) to tune stop cell hierarchy level and to enable timing characterization.
• Responsible for developing and updating quality check utilities to ensure quality of timing models.
• Engage with various teams to understand new STA requirements.
• Maintenance of the timing model databases.
• Evaluate best in class EDA tools and flow in the industry

PREFERRED EXPERIENCE:

• Have a solid understanding of MOSFET electrical characteristics and experience with transistor level circuit simulators, such as HSPICE and SPECTRE.
• Understanding of layout at the transistor level to effectively work with the mask design team. Familiarity with reviewing DRC and LVS results an added plus.
• Understanding or an ability to learn a wide variety of industry standard modeling formats including Liberty (CCS, NLDM and LVF), Verilog, LEF, Milkyway, NDM, CLIB and SPICE.
• Familiar with working in Linux environment, load sharing concepts (such as LSF) and version control (such as ICM) an added plus
• Experience designing or a solid understanding of standard cell architectures, including state retaining elements like latches and flops is an advantage.
• New colleague graduates are welcomed. Training will be provided.

• Cooperate and communicate well with the various stakeholders.
• Be self-motivated to continuously develop skills and accept a variety of responsibilities as a part of contributing to the design center’s success
• Demonstrate a positive attitude and respect for all members of the team
• Be willing to iteratively improve designs and repeatedly attempt to develop solutions to difficult problems.

ACADEMIC CREDENTIALS: 

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

LOCATION:

Singapore

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