Senior Principal Engineer

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Join Marvell’s Data Center Engineering (DCE) Connectivity DSP Team, where we innovate high-speed, low-power electrical and optical transceivers leveraging PAM4 and advanced modulation schemes with Forward Error Correction (FEC). Our cutting-edge DSP solutions enable the high-bandwidth interconnects that power AI, cloud, enterprise, and 5G infrastructure, forming the backbone of modern data centers.

As a High-Speed DSP Design Engineer, you will play a key role in micro-architecting and developing next-generation DSP architectures, collaborating with world-class engineers to deliver solutions that meet stringent performance, power, and area (PPA) requirements. This is your opportunity to contribute to system-level design and implementation in a leading technology group driving the future of connectivity.

What You Can Expect

• Work with DSP Architecture and Design teams to micro-architect high-speed DSP designs for connectivity systems.
• Research and evaluate architecture implementations to ensure they meet PPA (Performance, Power, Area) requirements.
• Collaborate closely with the verification team to ensure timely and thorough verification of DSP and digital designs to meet aggressive schedule deadlines.
• Drive design and implementation of adaptive DSP filters, MLSD (Viterbi) detectors, and other high-speed signal processing blocks.
• Develop cycle-accurate models and simulation environments for DSP algorithms and architectures.
• Optimize DSP designs for low latency, high throughput, and power efficiency.
• Provide technical leadership in RTL development, synthesis, timing closure, and integration of DSP blocks into SoCs.
• Support cross-functional teams including firmware, hardware, and SI/PI engineers to ensure robust system-level performance.

What We're Looking For

• Education: Master’s or Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field with extensive experience in digital signal processing (DSP) design and architecture.

• Experience: 15+ years in ASIC/SoC design, high-speed digital systems, and signal integrity/power integrity analysis.
• Expertise in:

-- Digital design for high-speed data paths, DSP implementations, and complex arithmetic circuits.
-- DSP filter adaptation implementation and Maximum-Likelihood Sequence (Viterbi) detector design (high-speed digital signal processing).

-- Gain, DC offset, Baseline wander correction implementation

-- Experience with forward error correction (FEC) and or CRC is a plus
-- Micro-architecture development, RTL design (SystemVerilog/Verilog), and verification using UVM.
-- ASIC design flow: floorplanning, synthesis, static timing analysis, LEC, CDC/RDC, and power analysis.

• Tools & Methodologies:

-- Proficiency with EDA tools for synthesis, timing, and verification.
-- Strong scripting skills (Python, TCL, Perl) for automation and modeling.

• Lab & Measurement:

-- Experience interpreting results from oscilloscopes, TDR, and other high-speed measurement equipment.

• Leadership & Communication:

-- Proven ability to lead & guide design teams, manage schedules, and deliver complex SoC projects.
-- Excellent technical writing and presentation skills.

Expected Base Pay Range (USD)

166,500 - 246,420, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity
 

As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.
 
Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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