This position offers a great opportunity to work on industry leading semiconductor devices, targeted for broad applications in Automotive and Industrial markets. In this role, you’ll be a member of DfT and Test Technology Development team, tasked with driving DfT and BiST technologies and solutions for NVM (Flash / OTP / EEPROM) and High-Speed Peripherals for Automotive and Industrial grade ICs. Knowledge of Analog / Mix Signal Blocks, DFT and test / HW design requirements and care abouts is a critical skillset needed to be successful in this role. End goal is to design and productize deep Analog and Mix Signal test solutions that are high in efficiency (DfT, test methods, complex ATE HW), enabling organization benchmarks in cost-of-test goals.
As a member of the “DfT and Technology Development” Product Engineering Team, you will be required to own, participate, lead, and drive below activities:
- Define Design-for-Test (DfT) and Built-In-Self-Test (BIST) techniques for complex NVM IP (Flash / OTP / RRAM, MRAM, etc.) working with design team.
- Definition of Design-for-Test (DfT) and Built-In-Self-Test (BIST) techniques for complex analog and digital designs working with design team.
- Define and code test automation, developing test program generation utilities, and creating golden test method libraries for current and new IPs.
- Identify, deploy company’s DFT/DFx standards and practices with a focus on improved quality and cost reduction.
- Develop and implement DFT methodologies and strategies for mixed-signal designs.
- Collaborate with cross-functional teams to ensure proper integration of DFT features into the overall design.
- Candidate is also expected to participate in Product DFT/Design Reviews at Pre-PG to define and outline ATE Capabilities, understand Product Spec requirements, outline test plan and requirements, keeping in mind ATE HW limitations and capabilities .
- Define and propose ATE solutions through “out-of-the-box” thinking during the product development. Drive for test solutions with maximal DfT and minimal test complexity (both hardware and software).
- Act as an interface between ATE vendor, BU PE and Design team to define DFT requirements, Test methods and checklists.
- you will be a member of a cross-functional team working on complex ATE testers (Advantest, Teradyne) to drive low cost of test solutions for complex / analog IPs, in high volume production testing.
- Having additional knowledge of High Speed Interfaces (PCIe, LVDS, CSI, DSI, QSPI, DDR, HDMI, USB, etc.), Power Management, massive multi-site, and/or I/Ps requiring Safety & Security is considered a HUGE PLUS. The candidate, in this role, is expected to learn protocols and industry standards for these high speed interfaces, define test methods for high-volume production testing with high parallelism, and build / code ATE test-plans for characterization and production testing.
- Drive efficient test methods for NVM such as Flash and test flow to enable entitlement test cost.
- Drive defect-based test methods.
- Architect hierarchical DFT solutions covering multiple clock and power domains.