Senior Design Engineer, HBM Base Design

Responsibilities will include, but are not limited to: Design and develop high-speed interface PHY and its sub-block such as high-speed paths, calibration, training, control, test, loopback, clock domain crossing, etc. Work with Pre/Post-silicon verification teams to test, debug, and root-cause RTL simulation/Silicon/System failures. Working knowledge of Synthesis, STA, Lint & CDC Working knowledge of DDR/LPDDR JEDEC protocol and DDR PHY designs Experience with micro-architecture and Asynchronous digital designs Experience with DDR training algorithms and data path designs Experience in domain transfer designs, APB/JTAG, DFI BSEE or greater 5+ years of relevant Engineering or Design Engineering experience