Job Details:

Job Description: 

About the Group:

Central Engineering Group (CEG) oversees all test chip design, all foundational and hard IP, all EDA and design platform functions for Intel Products, as well as all external IP and EDA commercial licensing. The Central Engineering group is also responsible for delivering industry-leading Custom Silicon Solutions for Intel Customers in the Client and Hyperscaler Domains.

About the Role:

We are seeking an experienced SoC and Systems Pre-Silicon Verification Architect to drive the verification strategy, methodology, and execution for complex SoC designs and x86 chiplet based System in package designs. The ideal candidate will define and lead the end-to-end pre-silicon verification architecture, ensuring first-pass silicon success through robust planning, scalable methodologies, and technical leadership across verification domains.

Key Responsibilities:

• Verification Architecture and Strategy Expert in driving verification methodologies for high-speed IPs and Chiplet-based designs Define a comprehensive System Verification Plan and develop auto-generated Test Bench components that improves team productivity Define the overall SoC-level verification strategy, including simulation, emulation, and formal verification approaches. Develop test plans and coverage models for system-level features, interconnect fabrics, coherency, power management, and security subsystems. Architect scalable UVM-based environments for SoC, Chiplets, and IP-level integration.
• SoC Integration and Verification Specializing in Design / Verification/ 3rd party IP Integration of High Speed Mixed Signal IP with a proven first-pass silicon success record Oversee integration of multiple IPs (PCIe Gen6/7, LDDR5/6, Ethernet, Security, etc.) into the SoC. Drive verification closure for interfaces such as AXI, ACE, CHI, and interconnect fabrics. Collaborate with IP and Chiplet design teams to define verification hooks, checkers, and assertions.
• Methodology Development Define and promote reusable verification methodologies (UVM, constrained-random, coverage-driven verification). Automate verification flows, regressions, and coverage analysis using industry-standard tools (Synopsys VCS, Cadence Xcelium). Lead verification infrastructure development including scoreboard, checkers, monitors, and VIP integration.
• Leadership and Collaboration Provide technical guidance and mentorship to DV engineers and subsystem leads. Work closely with architects, designers, validation, and firmware teams to ensure feature completeness and verification signoff. Lead cross-functional debug efforts during simulation, emulation, and silicon bring-up. Drive Emulation Methodology and the required models to support Xeon Co-Emulation
• Performance and Quality Emulation of Digital Design with Firmware, Python/C modeling for Architectural/Performance modeling Drive functional and code coverage closure for SoC-level verification. Define and maintain verification metrics and quality standards. Participate in post-silicon correlation and feedback to improve future verification methodologies.

Required Experience:

• Expertise in System Verilog, UVM/OVM methodologies.
• Deep understanding of SoC architecture, coherency protocols, cache subsystems, and interconnect fabrics.
• Strong knowledge of protocols like PCIe, DDR, AXI, CHI, or NoC.
• Experience with emulation and prototyping platforms (Palladium, Veloce, FPGA-based).
• Familiarity with power intent verification (UPF), security verification, and formal verification tools.

Preferred Skills

• Experience with PCIe, Security, SmartNIC, or heterogeneous compute SoCs.
• Exposure to AI/ML accelerators or custom interconnect fabrics.
• Strong scripting skills (Python, Perl, or TCL).
• Experience driving pre-silicon to post-silicon correlation.
• Excellent communication and technical leadership skills.
• Strong analytical and debugging skills.
• Demonstrated ability to lead cross-functional technical teams.
• Proven track record of delivering high-quality verification results on schedule.
• Passion for innovation and continuous improvement in verification methodologies.

Qualifications:

• MS in Electrical Engineering, Computer Engineering, or related field.
• 15+ years of experience in ASIC/FPGA/SoC development and pre-silicon verification
• 4+ years in a verification architect or technical lead role.
• Proven track record of leading verification for complex SoCs or high-performance IP subsystems.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, California, Santa Clara

Additional Locations:

Business group:

Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

 

 

Annual Salary Range for jobs which could be performed in the US:

 

 

$214,730.00-303,140.00 USD

 

 

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

 

 

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.