Lead Design Verification Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

About the Department:

Central DFX (CDFX) is a centralized ASIC design group within AMD’s Technology and Engineering organization. CDFX has a global footprint with design teams located in several AMD offices across North America and Asia. The team is responsible for developing and supporting DFX methodologies and automation tools for AMD’s cutting-edge APU, GPU, and game console products.

THE ROLE:

As a Lead Design Verification Engineer in the Central DFX team, you will play a key technical role in developing and executing verification strategies for complex semiconductor designs. You will contribute to the design and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features, and help optimize and standardize verification methodologies across AMD’s global engineering teams. This role emphasizes technical leadership, hands-on execution, and cross-functional collaboration.

THE PERSON:

You are a technically strong engineer who thrives in a fast-paced environment and enjoys solving complex verification challenges. You take initiative, work independently, and influence others through your expertise and collaboration. You are passionate about delivering high-quality designs and improving productization efficiency across AMD’s portfolio.

KEY RESPONSIBILITIES:

• Develop and execute comprehensive verification strategies for complex ASIC designs, with a focus on DFT and DFD features.
• Collaborate with design, architecture, and software teams to align on verification goals and resolve technical challenges.
• Contribute to the development and adoption of advanced verification methodologies and automation tools.
• Perform hands-on testbench development, simulation, coverage analysis, and debug using UVM and SystemVerilog.
• Drive quality assurance through rigorous reviews, metrics tracking, and continuous improvement of verification processes.
• Provide technical mentorship to junior engineers and share best practices across teams.
• Influence verification planning and execution across IP and system levels.

PREFERRED EXPERIENCE:

• Proven experience in ASIC design verification, especially in DFT/DFD domains.
• Strong hands-on skills with UVM, SystemVerilog, C++, and scripting languages.
• Experience integrating RTL and software solutions from IP to system level.
• Deep understanding of verification methodologies, coverage analysis, and debug techniques.
• Strong analytical and problem-solving skills, including design of experiments and root cause analysis.
• Excellent communication skills for cross-functional collaboration and documentation.
• Self-motivated and able to work independently while contributing to team goals.

ACADEMIC CREDENTIALS:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.