Support integration of process modules across various DRAM module loops. Analyze electrical and inline data to identify yield detractors and process anomalies. Collaborate with cross-functional teams (TD, PE, CPIE, OMT) to drive continuous improvement. Document findings and present updates to engineering and leadership teams. Currently pursuing a B.S, M.S or PhD. in Electrical Engineering, Materials Science, Chemical Engineering, or a related field. Strong analytical and problem-solving skills. Familiarity with semiconductor fabrication and process flows is a plus. Proficient in Excel, JMP, and data visualization tools. Excellent communication and teamwork abilities. 3-6 months (flexible based on academic calendar) Prior internship or lab experience in semiconductor manufacturing or process engineering. Knowledge of SPC, DOE, and yield analysis methodologies. Can start in January of 2026