Engineer II - Device Data Modeling

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Job Description:

• In depth knowledge of electrical engineering fundamentals including deep sub-micron CMOS device operation and characteristics, understanding of advancing modeling techniques
• Hands on experience with simulation using tools such as HSPICE, Finesim/PrimeSim or Spectre
• Understand any digital/mixed signal block such as SRAM, I/O using specification
  • Define timing arcs like setup, hold, propagation delay
  • Extract netlist through StarRCXT
  • Ability to write SPICE test bench (compatible to simulators like HSpice, FineSim, Spectre etc) for any digital block from the scratch.
• Write measurement statements to get required timing and power data
• Run simulations using SPICE simulator
• Expertise in Perl, Shell, TCL scripting

Secondary Skill Set

• Hands on experience with running PrimeTime, Tempus extracting timing data for custom PnR blocks
• Understand any custom ASIC blocks like Processor by reading spec
  • Define timing arcs like setup, hold, propagation delay
  • Extract SPEF netlist through StarRCXT
  • Define set case analysis statements to configure block in required modes
  • Back annotate SPEF and extract all the required timing data

Requirements/Qualifications:

• Exposure to Physical verification using LVS and LPE tools (Synopsys Hercules or Mentor Graphics Calibre and StarRC-XT)
• Exposure to Static Timing analysis at transistor level with tools such as NanoTime
• Exposure to Standard cell characterization tools such as SiliconSmart, Liberate
• Working knowledge of SOC and/or FPGA Architectures
• Knowledge of FPGA design synthesis and routing associated with Microchip (Libero), Xilinx (ISE), or Altera (Quartus) tools
• Working knowledge of ASIC/FPGA design flows with a focus on timing and power analysis tools
• Bachelor's or higher degree with 3+ years of experience.

Travel Time:

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