Manage and provide technical oversight for Compute DRAM design projects. Provide leadership across the DRAM design organization for all design related issues and drive toward commonality in all aspects of Compute DRAM Design. Manage Compute DRAM Design and Layout teams to develop and support DRAM products. Ensure teams have the resources they need, supervision, and guidance. Monitor their progress and help them meet their project goals. Provide design project management on any level including planning, scheduling and resource management. Provide technical supervision to engineers and project leads as part of project management responsibilities. Interface between Compute DRAM Design and CNBU (and other BU's if needed) by providing technical input on functions and features related to DDR5/DDR6, providing technical input to the BU on topics required to make business decisions (die size, schedule, etc.), attending DDR6 development activities (both internal and external) and driving the discussion where appropriate. Build a working relationship with other DRAM Design/PE pillars and help support their DRAM design efforts by sharing resources and information with them. BSEE or Greater, 15+ years of related experience 10+ years of design and circuit simulation experience using analog and digital tools 5+ years debugging circuits based on both simulation and silicon results within the semiconductor industry 5+ years of design team management at a semiconductor company Master's degree, MSEE, with 15+ years of experience in Electrical Engineering or a related technical field in the semiconductor industry A self-motivated, hard-working team player who enjoys working with diverse abilities and backgrounds Good interpersonal skills with the ability to convey sophisticated technical concepts to other design peers in verbal and written form 8 years of analysis and optimization of DRAM performance, power, and reliability metrics 8+ years of design team management at a semiconductor company