Circuit Design Verification Intern – DRAM Design

Performing verification processes with modeling and simulation using industry-standard simulators BSEE Student with 1 year to finish. Able to communicate in english, verbally and written Productive and efficient time usage thereby leading to more effective work. Satisfactory ability to convey or share ideas either verbally or in written form. Knowledge and experience with a hardware definition language (like System Verilog or VHDL) Experience with a scripting language (Python, Perl, Verilog, UVM, etc)