Chip Architect

We are seeking a talented Chip Architect to join our ACS team which develops cutting edge ASSP ICs. This individual will play a key role in architecting mixed-signal chips, partitioning digital and analog design blocks to optimize functionality and performance, especially for high-speed clock and data paths, and to drive best-practices in Design for Verification and Design for Test.

This individual will:

• Work with our customers, systems, analog/digital design, layout, verification, and test/validation teams to define the chip architecture to meet all project requirements.
• Own the chip top-level integration. Drive the integration process from architectural definition through PG, ensuring robust functionality, parametric compliance, and on-time first-pass success.   
• Partition functionality between analog and digital domains according to best-practices, to be rigorously verifiable (Design for Verification), and to be testable (Design for Test).
• Architect high-speed clock and data paths across analog and digital domains to meet chip performance objectives and to allow for robust sign-off. Define the methodology for sign-off of clock and data paths across analog and digital domains (e.g. CDC, RDC, formal, extractions, STA, margining, jitter, cross-talk, EMIR, aging, GLS, DMS, AMS, Spectre and Xcelium simulations, etc.).
• Enable rigorous DMS and AMS verification through design partitions that are friendly to modeling, and by driving a rigorous block modeling methodology. Create and maintain models and/or drive model creation with stakeholders. Create and maintain flows to manage netlisting and config hierarchy selection for AMS and DMS flows (e.g. schematic netlist, real-number model, simple logical model, Verilog-AMS electrical or wreal model, RTL, Gates/SDF, etc.).
• Define block handoff requirements and acceptance checks for analog IP and digital IP. Drive sign-off checks. Increase the use of automation to ensure consistency in results and to reduce manual effort.
• Effectively work with project management and cross-functional team members to ensure all project deliverables meet requirements and schedules, and to ensure smooth integration according to plan.