Development of TCAD process and device models to enable predictive analysis for advanced logic (FinFET, GAA, CFET) and DRAM architectures (6F2, 4F2 VCT and 3D DRAM) Development and modification of speculative process integration schemes and risk/benefit assessment. Extraction of compact model representation of TCAD simulated devices. Layout development/design of standard logic cells and DRAM array Interconnect modeling and parasitic resistance and capacitance extraction SPICE modeling and PPA projection for benchmark logic circuits & blocks and DRAM array / periphery Collaborate with cross-functional teams to define simulation requirements, interpret results, and provide actionable design and process recommendations. Support technology roadmap development by evaluating new materials, interconnect structures, process flows and design. Drive design-of-experiment (DOE) studies and sensitivity analyses to understand key drivers of electrical performance and reliability. Contribute to the development and automation of internal simulation workflows, tools, and best practices to improve modeling efficiency and accuracy. Document and present simulation methodologies, results, and recommendations to both technical and executive audiences. Stay current with industry trends, emerging technologies, and academic research in advanced packaging and simulation methodologies. Master's or Ph.D. in Electrical Engineering, Materials Science, Applied Physics, or a related field. 5-10 years of hands-on industry experience with Synopsys 3D TCAD process, device, parasitic extraction and spice modeling tools towards logic or memory technology development. Strong fundamental understanding of semiconductor device physics related to logic and DRAM technologies. Familiarity with logic (FinFET, GAA and CFET) and DRAM process integration flows (FEOL / MOL / BEOL) and 3D device structures. Experience with logic benchmark circuits and PPA evaluation methodologies. Experience with DRAM array and periphery operation. Experience with scripting and automation (e.g., Python, TCL, MATLAB) to streamline simulation workflows. Excellent analytical, problem-solving, and communication skills. Proven ability to work independently and collaboratively in a fast-paced, cross-functional environment. Strong problem-solving abilities in interdisciplinary areas Ability to present scientific and/or experimental results in a concise and convincing manner Desire to stay up to date with industry challenges and recent advancements Passionate and highly motivated to learn new things Experience with device and circuit level reliability modeling Recent experience with writing research papers for conference and journal publications Experience with standard cell characterization, RTL synthesis, DRC/LVS and place-and-route and timing analysis flows Experience in calibration to hardware/measurements and correlations