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Design Verification Senior Staff Engineer

pin iconAustin, Texas United States Apply Now
Category: Engineering Hire Type: Employee
Job ID 49825BR Salary Range 135000-203000 Date posted 04/24/2024
Our Silicon Lifecycle Management (SLM) business is all about building next-generation intelligent in-chip sensors, hardware/software capabilities and analytics to integrate into technology products to manage and improve each semiconductor lifecycle stage. We offer the world’s first full hardware IP, test, and end-to-end analytics to help customers integrate faster, optimize performance/power/area/schedule/yield, and enhance reliability. Meeting the unique challenges posed by various target applications, SLM enables differentiated products to market quickly with reduced risk.

The Digital R&D team within the HDG (Hardware Development group) is chartered with developing digital hardware IP that are crucial component of the SLM sensors.

Job responsibilities include:
  • Design verifications for digital sensor IP’s in development.
  • DV at RTL/Gate level; DV coverage analysis; coverage improvements.
  • Engage in gate level simulations; flow automation scripting; test plans.
  • Work with IP design engineers to fully enable new IP’s.
  • Capability contributing to design arch a plus.

Preferred Skills:
  • Languages: Verilog, SV.
  • Methodologies: UVM.
  • Scripting: makefile/Python.

Expertise Needed:
  • Involved in IP/SOC level verification.
  • Developed and maintained IP level UVM/SV environments.
  • Exposed to SV assertion-based verification.
  • Test planning and coverage closure.
  • Knowledge of Bus protocols like AXI, AHB, APB, JTAG.
  • Gate level Simulation experience.
  • Experience of developing SOC environments and C based testcases.
  • 5+ years of industry experience is highly desirable.
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At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

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The base salary range across the U.S. for this role is between $135,000-$203,000. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

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Synopsys Hiring Process 1. Apply. As an applicant, your resume, skills, and experience are being reviewed for consideration. 2. Phone screen. Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you and share more about the role. 3. Interview. You will be invited to meet with the hiring team to measure your qualifications for the role. Our interviews are held either in person or via zoom. 4. Offer. Congratulations! You have been selected as a finalist; your recruiter will reach out to propose your offer details. A written offer will soon follow. 5. Onboarding. You will be invited to complete new hire documents to ensure you are set-up and prepared for your first day. 6. Welcome. Your hiring manager, team, and an assigned buddy will help you get acclimated. Over the next few weeks, you will receive communications and engagement invitations that will help ramp you up for your future at synopsys

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