Job Description
NXP's MCU/MPU Engineering (MME) team is a central engineering organization responsible for developing and delivering Systems-on-a-Chip (SoCs) for NXP's Automotive, Secure Edge, Advanced Analog and Radar Processing business lines. MME's SoC Hardware Architecture team produces architectural solutions covering the very wide-range of SoCs required by the business lines. The team is challenged to produce industry-leading solutions covering very cost-sensitive, low power devices to highly-integrated, high performance, multi-domain devices compliant with the latest automotive and industrial safety and security standards.
Responsibilities
- Work with cross-functional teams to develop scalable SoC design and integration solutions across a wide-range of product types and tiers
- Define, design and integrate optimal SoC Infrastructure solutions for SoC and its sub-systems
- Work closely with adjacent SoC functional and Software teams to ensure SoC Infrastructure solutions conform to their needs across all product types
- Collaborate with Digital and Mixed-Signal IP, Design for Test and Quality teams throughout the entire product development cycle to ensure solution is successfully deployed in commercial product
- Constantly drive SoC Design and Integration efficiency improvements by closely collaborating with global Design Enablement and Design Automation teams
- Obtain profound understanding of current ways of working and identify opportunities for SoC execution cycles optimization
Required Skills
- Experience in designing or architecting complex SoCs in leading-edge process nodes with multiple independent compute environments
- Ability to work at the system-level, identifying optimal partitioning of solutions between hardware and software, working closely with various software teams
- Experience in defining Foundation IP components to support automation flows
- High motivation and results orientation
- Strong problem solving capabilities
- Excellent interpersonal skills, including written and verbal communication
- Great teamwork, and presentation abilities
- Self-driven with good leadership skills
- Willing and able to mentor junior engineers across multiple design centers
Job Qualifications
- BS/MS/PhD with 10+ years of experience in Semiconductor industry.
- Experience with System Verilog and front-end tooling (simulation, waveform viewers, lint, CDC, RDC, etc.) is required, as well as highly efficient FE methodologies.
- Must have worked on complex, multi-core SoC’s with extensive interconnects and a large range of peripherals.
- Strong domain knowledge of clocking, system modes, power management, debug, security and other architectures is a must.
- Must have strong track record of managing RTL design through several successful tape-outs.
- Familiarly with system design, Software concepts and SoC micro-architecture and/or design.
- Proficiency in C/C++, and scripting languages such as Python.
The base salary range for this position is as mentioned below per year. We also provide competitive benefits, incentive compensation, and/or equity for certain roles.
Company benefits include health. dental, and vision insurance. 401(k), and paid leave. Please note that the base salary range (OR hourly rate) is a guideline, and individual total compensation may vary based on a number of factors such as qualifications, skill level, work location, and other business and organizational needs. This base pay range is specific to California and is not applicable to other locations. A reasonable estimate of the base salary range as of the date of this posting is:
$204,000 to $280,400 annually
More information about NXP in the United States...
NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.