Director SoC Design (RTL and Verification)
Business Line Description
We are part of MCU/MPU Engineering, a central design organization within NXP, developing products for multiple business lines in Automotive, Internet of Things (IoT), Networking, and Radio Frequency products, with expertise in hardware engineering, including architecture, IP, and full SoC Design. This enables a product portfolio with over four billion USD in annual revenue. Chances are that the car you drive, the intelligent devices that pervade your living space and the factories that produce the goods you use will contain one or more of the SoC’s chips that you contribute to.
Job Summary:
Responsibilities include resource management, project scheduling, execution, and setting high-level technical vision. Projects span a variety of business lines, and designs will need to meet a wide range of power/performance/area goals, depending on the product. Engagement and collaboration across global sites is a key aspect of this role as alignment of methods is essential and sharing of resources is common. Strong technical, communication, and consensus building skills will be required as well as a demonstrated ability to influence solutions across a global organization. The ideal candidate will partner with local and global SoC teams to drive best practices with a target of productivity improvement.
Lead Soc RTL and Verification R&D team driving technical execution and best in class methodologies used in the design of advanced microcontrollers and microprocessors.
Fully own RTL delivery for a multitude of projects
In this role you will also lead and build this high performance SoC RTL and Verification team, including training and mentoring NCG’s and developing next level verification leads
Responsible for developing team members goals and development plans ensuring a high performing SoC verification team
Work closely with system architects to define high level specifications that are implementable and robust.
Interface with verification/validation teams to ensure design quality and robustness.
Work with various EDA vendors to deploy next generation tools
Build strong collaboration with other R&D teams such as Verification, digital IP, Design Enablement, Emulation, and Validation to achieve project milestones
Promote continuous improvement to design techniques to ensure ‘Zero Defect’ chips
Collaborate with SME’s and key leaders in architecture, systems, emulation, SoC design, software, physical design, and IP teams developing key technical networks to influence overall design improvements and verification methodologies
Responsible for developing detailed Technical SoC verification execution plans, including resource schedules, progress reports and tracking milestones, managing technical risks, and providing mitigations to meet schedule quality and costs commitments. Communicate across technical teas as well as provide executive level presentations
Complete ownership for SoC verification quality sign-offs ensuring all deliverables for team hand-offs.
Drive best in class verification methodologies collaborating with global internal and external SME’s and developing adoption and compliance processes. Including, driving key innovation strategies which significantly impact efficiency and quality for overall R&D and ROI
Participate in customer engagements assessing quality and risks
Key Challenges:
This role requires close collaboration across global teams for resolving SoC Verification methodology alignment, the leadership role needs to be strongly integrated locally as well as globally in order to make the right trade-offs in methodology and project execution
This role with have direct impact on product execution for business lines across Edge Processing, Auto Processing and RF Processing responsible for schedule, cost and quality commitments in SoC verification as well as identifying key improvements and ROI across the entire development process
Cross functional aspects:
VP and Directors in IP development to plan strategic SoC Verification dependencies, roadmaps and methodologies and strategic IP innovations
Chief Architects and Engineers for developing SoC Verification strategic roadmaps and managing execution deliverables from SoC Verification team
Directors in implementation, RTL, DFT, Emulation to collaborate on project development plans and execution and develop common methodologies
VP’s and directors in R&D and Business Lines to provide project status, strategic methodologies and tools.
Job Qualifications:
BS/MS/PhD with 15 years of experience in Semiconductor industry. Candidate should be an experienced manager with a history of leading successful SoC RTL and Verification teams.
Experience with System Verilog and front-end tooling (simulation, waveform viewers, lint, CDC, RDC, etc.) is required, as well as highly efficient FE methodologies.
Must have worked on complex, multi-core SoC’s with extensive interconnects and a large range of peripherals.
Strong domain knowledge of clocking, system modes, power management, debug, security and other architectures is a must.
Any of following experience would be a plus: High Speed Peripherals like DDR, PCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memory subsystems.
Must have strong track record of managing RTL design through several successful tapeouts.
Location:
More information about NXP in the United States...
NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.