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Job Description:
VLSI Design SOC/TOP level engineer with 7-10 years of experience in RTL Design /Integration skills
He/she should have strong knowledge of following
- Verilog RTL/System Verilog coding
- SOC/Top-Level integration flows ( integrating multiple IPs and associated, clock domains )
- Synthesis ( DC ) and Timing Concepts (STA)
- Spyglass ( lint, DFT, PM, CLK/RST, CDC)
- Formal Verification , Conformal LEC)
- Perl scripting
CAD Tools : Cadence/Synopsys
Mandatory skills :SOC/Top-Level Design /Integration,Implementation
Optional Domains skills : Any networking protocol ,Ethernet, PICe or CPU
Education Qualification : Bachelor’s/Master’s in Electronics/Computer Engg
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
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