Job Description
Intel's Advanced Design (AD) team is part of the larger Design Enablement (DE) organization that is focused on pathfinding and the development of advanced memory and circuit technology to enable best-in-class memory collateral and product design across all generations of Intel process technology. You will be one of the first people to run design flows on Intel's newest technology and be positioned to influence how the technology and design methodologies are defined for Intel.
As part of the DMA team within AD, you will work on enabling the static timing methodology for the latest silicon technology using industry standard and custom tools. This role will encompass enabling, qualifying, and debugging Static Timing (STA) tools and flows for custom and synthesized blocks, through automation/scripting and manual testing, on a research team that focuses on enabling Intel technology. You will be one of the first people to run design flows on Intel's newest technology and be positioned to influence how the technology and design methodologies are defined for Intel. Design Automation Engineers are advocates of applying design methodologies to help execute projects effectively and successfully with high quality.
Responsibilities include but are not limited to the following:
Enabling the flows in new environments/technologies.
Writing unit-level tests for continuous integration in a design environment.
Writing automation that can identify quality issues.
Help users with corner cases to find workarounds and find ways to create self-service troubleshooting.
Explore ways to automate more tasks to make the flows more efficient and help save user time and effort.
#DesignEnablement
Qualifications
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work/classes /research and/or relevant previous job and/or internship experiences.
Minimum Qualifications:
Candidate must possess a degree in Electrical Engineering, or Computer Engineering: Bachelor's with 4+ years, Master's with 3+ years, or PhD with 1+ years of experience working with/Enabling Static Timing Analysis tools for design/ std cell library characterization.
Preferred Qualifications:
Good understanding of static timing fundamentals.
Knowledge of the typical RTL-APR flow: RTL, simulation, validation, synthesis, APR, extraction, and timing/characterization.
Debugging of Synopsys digital design tools and flows (PrimeTime/NanoTime, Finesim).
UNIX shell, Perl, or Python scripting.
#designenablement
Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits
here.Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
In certain circumstances the work model may change to accommodate business needs.