Job Description
As a member of the Logic Design and Validation group within the Lead Vehicle Development group in Design Enablement you will be part of a team that develops the RTL models and pre-silicon validation tests for test chips on the next generation Intel silicon manufacturing process. Your responsibilities would include:
Creating new digital, analog, and mixed-signal RTL models for new and existing designs
Running the Functional Equivalence Verification (FEV) flow to compare RTL to schematics
Owning the creation of pre-silicon validation test plans, formal SystemVerilog/UVM testbenches, and validation test cases
Owning RTL design of new digital systems ranging from design-for-test (DFT) on existing systems to novel designs to enable Power-Performance-Area (PPA) studies on next-generation technology nodes.
The ideal candidate should exhibit the following behavioral traits:
Motivated, driven, with sense of urgency and commitment to achieve targeted goals
Communication and problem-solving skills
Documentation, and presentation skills
Troubleshooting and analytical skills
#DesignEnablement
Qualifications
Minimum Requirements
Candidate must possess a Master's degree in Electrical Engineering, Computer Engineering or related fields of study with a minimum of 4 year of experience listed below or a Bachelor's degree in Electrical Engineering, Computer Engineering or related fields of study with a minimum of 7 years of experience in the following:
Performing Pre-Silicon Logic Validation at Unit level or Integration level
Digital design using Verilog and System Verilog
Pre-silicon logic validation closure for multiple projects/designs
OVM/UVM, preferably in testbench design and setup for reusability
Defining overall validation approach for complex digital system and execution of those plans
System Verilog Assertions (SVA), their creation and application in closing validation coverage
Coverage-based verification and how to leverage for efficient validation closure.
Preferred Requirements
Minimum of 1 year of experience with analog circuits and their interaction with digital systems
Minimum of 1 year of experience in Unified Power Format (UPF) specification
Experience with scripting and automation with languages such as Perl or Python
#designenablement
Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits
here.Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
In certain circumstances the work model may change to accommodate business needs.