Analog Mixed-Signal Design Engineer

ENGINEERING – CIS Santa Clara, California


Description

  • Design, develop, and characterize embedded analog circuits, such as high speed I/O, SerDes, FIFO, CDR, PLL, etc.
  • Design and debug RTL level signal synchronization, clock tree and conduct cross domain clock designs. 
  • Work closely with system and test engineers to develop high speed interface, package/board, and system clocks in image sensor and bridge chip products.
  • Conduct Layout design and support.  Get involved into layout optimizations for high speed or high precision performance directly.  Use Cadence analog design/layout flow and spice/spectreMDL simulations.
  • Perform transistor level integrated circuit design and simulation.  Develop clock generator and distribution tree circuits with low jitter and low duty-cycle distortion.  Perform transistor level design of serializer circuit which works up to Gbps data rate within process and temperature corners.  Design accurate analog biasing and reference circuit for IO links.  Characterize the IO links circuit performance under non-ideal environment (high power supply noise, crosstalk, process variation and mismatches). Use software: Cadence Virtuoso, Cadence Spectre simulator and AFS simulators.
  • Debug and design change solutions on signal integrity, EMI/RFI., ESD/latch up issues.  Develop the floor-plan of IO link that is friendly to signal-integrity. Develop and improve ESD circuit on the IC chip to pass industry ESD standards.
 
Job Requirements:
 
MS in Electrical Engineering, Computer Engineering, or related field with coursework in VLSI Design, Analog Integrated Circuit, and M-Wave Circuit.
 
Possess the following skills:
  • Analog Circuit Design.
  • Circuit debugging skills.
  • Detailed analysis and design of analog integrated circuits, including power amplifiers, voltage references, voltage regulators, rectifiers, oscillators, multipliers, mixers, phase detectors, and phaselocked loops.
  • Implement the Design to specification including behavioral modeling with Verilog/Verilog-AMS or System Verilog.
  • Integrated circuit fabrication technologies and BJT and MOS transistor models.
  • Linux/UNIX tools, such as grep, awk and vi for creating and editing of EDA tool input files as well as analyzing of EDA tool report files.
  • Spice Simulators with statistical variation: HSPICE with Monte Carlo simulation variation analysis.
  • RTL design, coding, simulation, verification, and/or place/route.
  • Utilizing Tcl Perl Python scripting for physical design data mining and flow customization.
 
Annual base salary for this role in California, US is expected to be between $ 151,091- $155,000.
Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.